Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.

BACKGROUND OF THE INVENTION

This invention relates to a method of manufacturing a semiconductordevice, and more particularly to a manufacturing technique ofstabilizing an operation of writing information into each of elementswhich constitute a mask ROM (Read Only Memory).

In order to shorten the TAT (Turn Around Time) of a mask ROM, varioustechniques of ion-implanting for writing information (which is alsoreferred to as “program write” or “ROM write”) after an Al wiring hasbeen formed are known. Referring to FIGS. 9A to 9D, an explanation willbe given of a conventional manufacturing technique.

Step 1: As seen from FIG. 9A, using the technique of thermal oxidationor CVD, a pad oxide film 72 of a silicon oxide film having a thicknessof 25 nm is formed on a P-type semiconductor substrate 71. The pad oxidefilm 72 is formed to protect the surface of the semiconductor substrate71.

Next, a silicon nitride film 73 which is an oxidation-resistant film isformed on the entire surface. Thereafter, lengthy stripes of openings 73a for forming element isolation films 74 are formed in the siliconnitride film 73 in a direction perpendicular to a paper face of thisdrawing.

Step 2: As seen from FIG. 9B, using the technique of LOCOS with thesilicon nitride film 73 as a mask, the semiconductor substrate 71 isoxidized to form element isolation films 74. At this time, oxide regionsinvades between the semiconductor substrate 71 and silicon nitride film73 so that bird's beaks 74 a are formed. Next, the silicon nitride film73 and pad oxide film 72 are removed, and using the technique of thermaloxidation, a gate insulated film 75 having a thickness of 14 nm to 17 nmis formed. Using the technique of CVD, a poly-Si film having a thicknessof 350 nm is formed, and phosphorus is doped to form an N-typeconductive film 76.

Step 3: As seen from FIG. 9C, the conductive film 76 is etched inlengthy strips in a direction orthogonal to the element isolation films74 (it should be noted that the etched region, which is in parallel tothe paper face, is not illustrated) to form gate electrodes 76 a. Usingthe gate electrodes 76 a as a mask, P-type impurities such as boron areion-implanted to form a source region and a drain region (which are notillustrated since they are formed below both ends of the gate electrodein a direction perpendicular to the paper face).

Through the process described above, memory cell transistors arranged ina matrix shape are formed. An interlayer insulating film 77 having athickness of 500 nm of a silicon oxide film is formed on the entiresurface. Al wirings 78 in lengthy strips, which serve as bit lines, areformed above the element isolation films 74, respectively in a directionperpendicular to the paper face. Until this step, the manufacturingprocess can be carried out irrespectively of what program should bewritten in the memory cell transistors. For this reason, the wafers canbe previously manufactured. In this case, a silicon oxide film 79serving as a protection film is formed on the entire surface.

Step 4: At the time when a program to be written is determined onreceipt of a request from a customer, as seen from FIG. 9D, aphotoresist 80 having openings 80 a for writing a program for a mask ROMis formed. P type impurities such as boron are ion-implanted in thesemiconductor substrate 71 immediately beneath the gate electrodes 76 afrom the openings 80 a so that predetermined memory cell transistors aredepleted. Thus, the threshold voltages of the memory cell transistorsare lowered so that a ROM data is written.

However, generally, the processing accuracy of the photoresist is low,e.g. 0.5 μm. Therefore, the openings 80 a formed in the photoresist 80provide a variation of 0.5 μm. Further, as described above, the elementisolation film 54 has the bird's beak and hence is thinned at its end.Therefore, where there is a variation in the openings 80 a, as seen fromFIG. 10, as the case may be, implanted impurity ions penetrate thebird's beak 74 a to reach the semiconductor substrate 71 beneath theelement isolation film 74, surrounded by circle A. Where such elementsare adjacent to each other, a leak current flowing below the elementisolation film 74, as indicated by arrow, occurs between the adjacentelements. This leads to poor element isolation. The improvement of theprocessing accuracy of the photoresist mask leads to a great increase incost.

Further, in the semiconductor device incorporating various transistorshaving different withstand voltages, the thickness of the gate insulatedfilm is set according to the various transistors. For example, where thegate insulated films having two kinds of film thicknesses are to beformed, a thick gate insulated film is once formed on the entiresurface, and is etched at the area(s) where a thin gate insulated filmis to be formed, and further the thin gate insulated film is formedagain.

In this case, when the thick gate insulated film is etched away, theelement isolation film will be shaved. During such a process, thethickness of the element isolation film at an ROM part gradually becomesthin.

In the process in which the ROM will be made later, ion-implantation fordata write is executed to penetrate an interlayer insulating film, gateelectrode and gate insulated film. Therefore, this must be carried outat high energy of 1 MeV to 3 MeV. The ion implantation at such highenergy increases the lateral diffusion of implanted ions. This alsoleads to the poor element isolation as described.

Further, the apparatus for executing ion-implantation at such highenergy is generally expensive, which results in an increase in cost.

For the reasons described above, in order to prevent the poor elementisolation, the element isolation film must be set in a width larger thana processing limit so as to give sufficient allowance. In addition, itis difficult to thin the element isolation film, which hindersminiaturization.

In order to overcome such an inconvenience, the above technique ofwriting information is carried out using as a mask the metallic film (Alwiring) with higher accuracy than the photoresist.

Referring to FIG. 11, the problem in the process using such a metallicfilm as a mask will be explained. FIG. 11 illustrates a semiconductordevice having a multiplayer wiring structure including Al wirings 78, 82and 84.

When interlayer insulating films are etched using the photoresist (notshown) as a mask, an Al wiring 78 also serves as a mask. Therefore, asseen from FIG. 11, a part of an interlayer insulating film 77 as well asthe interlayer insulating films 85, 83 and 81 on the Al wiring 78 isetched. At this time, the Al wiring 78 itself is also etched slightly.Thus, a deposit 86 is formed on the side wall of an opening 85 a. As aresult of analysis, it was found that the deposit 86 contains an etchinggas (e.g. BCl₃), carbon (C) contained in the photoresist and metallicwiring (Al), etc.

Owing to the presence of the deposit 86 on the side wall, the coveragewhen a passivation film 87 is deposited deteriorates (area surrounded bycircle B in FIG. 11). This presents a problem in reliability such asoccurrence of pin holes, attenuation of moisture resistance, etc. Inaddition, the sectional area of the Al wiring is also reduced so thatthe life of electromigration also attenuates. This is the first problem.

Further, in the process of writing information using the Al wiring as amask, in many cases, a flattened interlayer insulating film is formed onthe Al wiring 78. The flattened interlayer insulating film can be formedas shown in FIG. 12A, i.e. in such a manner that after a silicon oxidefilm 91 and spin-on-glass film (hereinafter referred to as SOG film) 92have been formed, the SOG film 92 is etched back, and a silicon oxidefilm 93 is formed.

In this process, if a wide Al wiring 78A (having a width e.g. 15 μm ormore) exists on the periphery of a random logic section and memorysection, under the influence of the wide Al wiring 78A, the SOG film 92becomes excessively thick on the periphery.

Thus, when the region to be information-written is etched to form anopening, as seen from FIG. 12B, an etching remainder 95 occurs becauseof the SOG film 92 thickened excessively. As a result, the diameter ofthe opening for writing information in the via hole or the ROM sectionruns short, thereby lowering the yield.

It is possible to suppress occurrence of the etching remainder bylengthening the etching quantity (time). However, in this case, the Alwiring itself serving as a mask is somewhat etched. In this case,although the deposit is formed on the side wall of the opening, it isnot problematic as long as the etching quantity is set appropriately.However, in order to suppress the etching remainder, if an excessiveetching quantity (time) is set, the deposit on the sidewall has anadverse effect. Owing to the presence of the deposit on the sidewall,the coverage when a passivation film is deposited deteriorates. Thispresents a problem in reliability such as occurrence of pin holes,attenuation of moisture resistance, etc. In addition, the sectional areaof the Al wiring is also reduced so that the life of electromigrationalso attenuates.

For this reason, in order to suppress the occurrence of the etchingremainder, the etching quantity (time) cannot be lengthened excessively.This is a second problem.

SUMMARY OF THE INVENTION

In view of the first problem, the semiconductor device according to thisinvention comprises: a gate electrode on a semiconductor substratethrough a gate insulated film; source/drain regions to be adjacent tosaid gate electrode; and a metallic wiring through an interlayerinsulating film covering said gate electrode, wherein impurity ions areimplanted into a surface of said semiconductor substrate with saidinterlayer insulating film being partially etched using as a mask saidmetallic wiring and a photoresist formed thereon, and a protection filmwhen said interlayer has been etched is formed on said metallic wiring.

Preferably, said protection film is a titanium film or a laminated filmincluding the titanium film and a titanium nitride film.

The method of manufacturing a semiconductor device according to thisinvention has a feature that said interlayer insulating film is etchedso that a surface of said metallic wiring is not exposed using aprotection film formed on said metallic film.

The method of manufacturing a semiconductor device has features thatsaid metallic wiring is formed in a multiplayer wiring structure, andthe impurity ions are implanted using the metallic wiring as a mask in astate where said interlayer insulating film has been etched using aphotoresist as a mask so that the surface of said metallic wiring is notexposed using a protection film formed on said metallic film at alowermost layer.

The method of manufacturing a semiconductor device has a feature thatthe impurity ions are implanted to write information in each of elementswhich constitute a mask ROM.

In the above configurations, when the interlayer insulating film isetched using the metallic film as a mask, it is etched so that saidmetallic wiring is not exposed using a protection film formed on saidmetallic film. For this reason, it is possible to prevent a deposit frombeing formed on the side wall of the opening of the interlayerinsulating film.

In view of the second problem, the semiconductor device according tothis invention comprises: a gate electrode on a semiconductor substratethrough a gate insulated film; source/drain regions to be adjacent tosaid gate electrode; a narrow metallic wiring and a wide metallic wiringthrough an lower interlayer insulating film covering said gateelectrode; and an upper interlayer insulating film formed to cover saidmetallic wirings and flattened; wherein impurity ions are implanted intoa surface of said semi conductor substrate with said interlayerinsulating films being etched by a prescribed amount using as a masksaid metallic wirings and a photoresist formed thereabove, and a grooveis formed in a surface of said wide metallic wiring.

Preferably, slits are formed at regular intervals so as to-subdividesaid wide metallic wiring.

The method of manufacturing a semiconductor device according to thisinvention comprises the step of forming said upper interlayer insulatingfilm so that a flattened film is embedded in a groove formed in asurface of said wide metallic wiring.

The method of manufacturing a semiconductor device has a feature thatsaid overlying insulating film is formed so that said flattened film isembedded in said slits formed at regular intervals to subdivide saidwide metallic wiring.

The method of manufacturing a semiconductor device has a feature thatthe impurity ions are implanted to write information in each of elementswhich constitute a mask ROM.

In this configurations, the flattened film is embedded in the groove orslits so that it is not formed excessively thick on the periphery of thewide metallic wiring. For this reason, shortage of the opening due tothe etching remainder can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are sectional views for explaining a method ofmanufacturing a semiconductor device according to a first embodiment ofthis invention;

FIGS. 2A and 2B are sectional views for explaining a method ofmanufacturing a semiconductor device according to the first embodimentof this invention;

FIGS. 3A and 3B are sectional views for explaining a method ofmanufacturing a semiconductor device according to the first embodimentof this invention;

FIGS. 4A and 4B are sectional views for explaining a method ofmanufacturing a semiconductor device according to the first embodimentof this invention;

FIGS. 5A to 5C are sectional views for explaining a method ofmanufacturing a semiconductor device according to a second embodiment ofthis invention;

FIGS. 6A to 6C are sectional views for explaining a method ofmanufacturing a semiconductor device according to the second embodimentof this invention;

FIGS. 7A and 7B are sectional views for explaining a method ofmanufacturing a semiconductor device according to the second embodimentof this invention;

FIGS. 8A and 8B are sectional views for explaining a method ofmanufacturing a semiconductor device according to a third embodiment ofthis invention;

FIGS. 9A to 9D are sectional views for explaining a method ofmanufacturing a conventional semiconductor device;

FIG. 10 is a sectional view for explaining a method of manufacturing thesemiconductor device;

FIG. 11 is a sectional view for explaining the first problem in theconventional semiconductor device; and

FIGS. 12A and 12B are sectional views for explaining the second problemin the conventional semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Now referring to the drawings, preferred embodiments of the inventionwill be described below.

Embodiment 1

Step 1: As seen from FIG. 1A, like the step 1 in the conventionalmanufacturing process, a pad oxide film 2 is formed on a P-typesemiconductor substrate 1 and a silicon nitride film 3 having openingsis formed.

Step 2: As seen from FIG. 1B, using the technique of LOCOS with thesilicon nitride film 3 as a mask, the semiconductor substrate 1 isoxidized to form element isolation films 4.

Next, the pad oxide film 2 and the silicon nitride film 3 are removed,and using the technique of thermal oxidation, a gate insulated film 5having a thickness of 14 nm to 17 nm is formed. Using the technique ofCVD, a poly-Si film having a thickness of 100 nm is formed, andphosphorus is doped to form an N-type conductive film 6.

A silicide film 7 of refractory metal such as tungsten having athickness of 150 nm is formed. The silicide film 7 as well as theconductive film 6 constitutes a gate electrode, and serves to reduce theelectric resistance of the gate electrode and protect the gate electrodeas described later.

Step 3: As seen from FIG. 1C, the conductive film 6 and silicide film 7are etched in lengthy strips in a direction orthogonal to the elementisolation films 4 (it should be noted that the etched region, which isin parallel to the paper face, is not illustrated) to form gateelectrodes 8.

Using the gate electrodes 8 as a mask, P-type impurities such as boronare ion-implanted to form a source region and a drain region (which arenot illustrated since they are formed below both ends of the gateelectrode in a direction perpendicular to the paper face).

Through the process described above, memory cell transistors arranged ina matrix shape are formed.

By the technique of CVD, an interlayer insulating film 14, whichincludes a silicon oxide film 10, a silicon nitride film 11, a poly-Sifilm 12 and a silicon oxide film 13, and has a thickness of 600 nm, isformed on the entire surface. The poly-Si film 12 serves as an etchingstopper when the interlayer insulating film 14 is etched as describedlater.

Step 4: As seen from FIG. 2A, a metallic film of an Al film is formed onthe interlayer insulating film 14. The metallic film is patterned toform Al wirings 15 which serve as word lines.

This step is a step which is a feature of this invention. First, themetallic film of an Al film having a thickness of 500 nm is formed onthe interlayer insulating film 14. Next, a titanium film having athickness of 70 nm is formed on the metallic film. A titanium nitridefilm having a thickness of 35 nm is formed thereon to constitute aprotection film. These films are patterned to form the Al wirings 15which serve as the word lines. In this way, in accordance with thisinvention, since the protection film 17 is formed on the Al wiring 15,when the interlayer insulating film is etched using the Al wiring 15 asa mask as described later, the Al wiring 15 is not etched because of thepresence of the protection film 17. Therefore, unlike the backgroundart, the deposit 86 is not formed on the side wall of the opening 85 aof the interlayer insulating film (see FIG. 11).

It should be noted that the Al wiring 15 is formed so that its edges 15a are located immediately above those of the element isolation film 4.Incidentally, the Al wirings 15 may be a composite film including themetallic film and an titanium film having a thickness of 20 nm and abarrier metal film of a titanium nitride film having a thickness of 35nm which underlie the metallic film.

In this way, in accordance with this invention, since at least theprotection film 17, which generally has a thickness (70 nm) sufficientlylarger than that (20 nm) of the titanium film which is used as the abovebarrier metal film, is formed on the Al wiring 15, the protection film17 serves as an etching stopper when the interlayer insulating film isetched using the Al wiring 15 as a mask. Incidentally, the thickness ofthe titanium film can be optionally set according to the etchingquantity of the interlayer insulating film.

Step 5: As seen from FIG. 2B, a second interlayer insulating film 23having a thickness of 600 nm and including three layers: a silicon oxidefilm 20, an SOG film 21 and another silicon oxide film 22 is formed onthe entire surface for flattening the surface. A metallic wiring such asan Al wiring is formed on the interlayer insulating film 23. Themetallic film is patterned to form a second Al wiring 24 which is a bitline.

Step 6: As seen from FIG. 3A, a third interlayer insulating film 25having a thickness of 600 nm is formed on the entire surface so as tocover the second Al wiring 24. A metallic wiring of an Al wiring isformed on the interlayer insulating film 25. The metallic wiring thusformed is patterned to form a third wiring 26.

Until this step, the manufacturing process can be carried outirrespectively of what program should be written in the memory celltransistors. For this reason, the wafers can be previously manufactured.In this case, in order to protect the metallic wiring layer and preventits corrosion, a protection film 27 of e.g. a thin silicon oxide filmhaving a thickness of 50 nm is formed on the entire surface.

Step 7: At the time when a program to be written is determined onreceipt of a request from a customer, a photoresist 29 is formed on thefourth interlayer insulating film 28 formed on the entire surface.Thereafter, using the photoresist 29 as a mask, the interlayerinsulating films are etched to make an opening 28 a in the region abovea prescribed memory cell to be program-written. Incidentally, it shouldbe noted that the etching is stopped on the poly-Si film 12 (FIG. 3B).

In this etching process, since the protection film 17 has been formed onthe Al wiring 15 as described above, unlike the background art, the Alwiring 15 itself is not etched and hence no deposit is formed on theside wall of the opening 28 a. For this reason, the coverage when apassivation film is formed as described later is improved. As a result,occurrence of pin holes is suppressed and moisture resistance isimproved so that the problem in reliability can be solved. In addition,since the sectional area of the Al wiring is not reduced, attenuation inthe life of electromigration can be suppressed.

The above suppression of occurrence of the deposit permits a contactresistance to be stabilized.

Further, by making the protection film 17 as a laminate film including atitanium film and a titanium nitride film, the etching of the Al wiring15 is prevented. Such a laminate film is also effective as a measureagainst a silicon nodule and as an anti-reflection film.

Incidentally, in this embodiment, the protection film 17 should not belimited to the titanium film used in this embodiment, but may be made ofany material as long as it has higher selectivity for the interlayerinsulating film than the Al wiring.

Further, as seen from FIG. 4A, P type impurities such as boron areion-implanted in the semiconductor substrate 1 immediately beneath thegate electrode 8 from the opening 28 a so that predetermined memory celltransistor is depleted. As described above, since the edges 15 a of theAl wiring 15 are located immediately above those of the elementisolation film 4, using the Al wiring as a mask, the ion implantationcan be carried out with great accuracy. Thus, the threshold voltage ofthe memory cell transistor is lowered so that a ROM data is written.

In addition, in accordance with this invention, in the write of the ROMdata, since the metallic film (Al wiring 15) having higher processingaccuracy than the conventional photoresist, unlike the background art,it is not necessary to give sufficient allowance in order to avoidoccurrence of poor element isolation and to give the element isolationfilm a larger width than the processing limit. This permitsmicro-structuring. Incidentally, the processing accuracy of thephotoresist is e.g. 0.5 μm, whereas the processing accuracy of the metalfilm is e.g. 0.1 μm.

Since a part of the interlayer insulating film 14 as well as theinterlayer insulating films 23, 25 and 28 on the Al wiring has beenetched, the ion-implanting can be carried out at low energy of 130 keVto 160 keV. This prevents the lateral diffusion of implanted ions, andhence permits the ion-implanting with higher accuracy.

Step 8: As seen from FIG. 4B, a passivation film 30 is formed on theentire surface. Thus, a mask ROM with a desired program written iscompleted. In this case, since the protection film 17 has been formed onthe Al wiring 15, when the interlayer insulating films are etched usingthe Al wiring 15 as a mask, the Al wiring 15 itself is not etched sothat no deposit is formed on the side wall of the opening 28 a. For thisreason, the coverage of the passivation film 31 will not deteriorate.

Embodiment 2

Now referring to the drawings, an explanation will be given of a secondembodiment of this invention.

Step 1: As seen from FIG. 5A, like the step 1 in the conventionalmanufacturing process and step 1 in the manufacturing process in thefirst embodiment, a pad oxide film 32 is formed on a P-typesemiconductor substrate 1 and a silicon nitride film 33 having openingsis formed.

Step 2: As seen from FIG. 5B, using the technique of LOCOS with thesilicon nitride film 33 as a mask, the semiconductor substrate 31 isoxidized to form element isolation films 34.

Next, the pad oxide film 32 and the silicon nitride film 33 are removed,and using the technique of thermal oxidation, a gate insulated film 35having a thickness of 14 nm to 17 nm is formed. Using the technique ofCVD, a poly-Si film having a thickness of 100 nm is formed, andphosphorus is doped to form an N-type conductive film 36.

A silicide film 37 of refractory metal such as tungsten having athickness of 150 nm is formed. The silicide film 37 as well as theconductive film 36 constitutes a gate electrode, and serves to reducethe electric resistance of the gate electrode and protect it asdescribed later.

Step 3: As seen from FIG. 5C, the conductive film 6 and silicide film 7are etched in lengthy strips in a direction orthogonal to the elementisolation films 34 (it should be noted that the etched region, which isin parallel to the paper face, is not illustrated) to form gateelectrodes 38.

Using the gate electrodes 38 as a mask, P-type impurities such as boronare ion-implanted to form a source region and a drain region (which arenot illustrated since they are formed below both ends of the gateelectrode in a direction perpendicular to the paper face).

Through the process described above, memory cell transistors arranged ina matrix shape are formed.

By the technique of CVD, a first interlayer insulating film 44, whichincludes a silicon oxide film 40, a silicon nitride film 41, a poly-Sifilm 42 and a silicon oxide film 43, and has a thickness of 600 nm, isformed on the entire surface. The poly-Si film 42 serves as an etchingstopper when the interlayer insulating film 14 is etched as describedlater.

Step 4: As seen from FIG. 6A, a metallic film of e.g. an Al film isformed on the interlayer insulating film 44. The metallic film ispatterned to form first Al wirings 45 which serve as word lines.

This step is a step which is a feature of this invention. Specifically,first, a metallic film of e.g. an Al film having a thickness of 500 nmis formed on the interlayer insulating film 44. Using a photoresist notshown as a mask, the metallic film is patterned to Al wirings 45 whichserve as word lines and a wide Al wiring 45A (having a width of e.g. 15μm or more) on the periphery of a random logic section and memorysection. Using a photoresist 46 as a mask, the Al wirings are patternedto form a groove 47 having a prescribed depth in the surface of the Alwiring 45A. Incidentally, although only one groove 47 is illustrated,actually, these grooves are formed at regular intervals according to thesize of the wide Al wiring 45A.

It should be noted that the Al wiring 45 is formed so that its edges arelocated immediately above those of the element isolation film 34.Incidentally, the Al wirings 45 and 45A may be a composite filmincluding the metallic film and an titanium film having a thickness of20 nm and a barrier metal film of a titanium nitride film having athickness of 35 nm which underlie the metallic film.

Step 5: As seen from FIG. 6B, a silicon oxide film 48 is formed on theentire surface, and an SOG film 49 is formed for flattening the surface.As seen from FIG. 6C, after the SOG film 49 has been etched back, asilicon oxide film 50 is formed so that a second interlayer insulatingfilm 51 including three layers and having a thickness of 600 nm isformed.

Step 6: As seen from FIG. 7A, a metallic film of e.g. an Al film isformed on the interlayer insulating film 51. The metallic film ispatterned to form second Al wirings (not shown) which serve as bitlines. A third interlayer insulating film 52 having a thickness of 600nm is formed on the surface so as to cover the second Al wirings. Ametallic film of e.g. an Al film is formed on the third interlayerinsulating film 52 is formed. The metallic film is patterned to formthird Al wirings (not shown). Then, a fourth interlayer insulating film53 having a thickness of 600 nm is formed on the surface so as to coverthe third Al wirings.

Until this step, the manufacturing process can be carried outirrespectively of what program should be written in the memory celltransistors. For this reason, the wafers can be previously manufactured.In this case, in order to protect the metallic wiring layer and preventits corrosion, a protection film of e.g. a thin silicon oxide filmhaving a thickness of 50 nm is formed on the entire surface.

Step 7: At the time when a program to be written is determined onreceipt of a request from a customer, a photoresist 54 is formed on thefourth inter layer insulating film 53 formed on the entire surface.Thereafter, using the photoresist 54 as a mask, the interlayerinsulating films are etched to make an opening 54 a in the region abovea prescribed memory cell to be program-written and a via hole 54 b to bein contact with the Al wiring 45. Incidentally, it should be noted thatthe etching for making the opening 54 a is stopped on the poly-Si film42 (FIG. 7B).

Step 8: As seen from FIG. 7B, P type impurities such as boron areion-implanted in the semiconductor substrate 31 immediately beneath thegate electrode 38 from the opening 54 a so that a predetermined memorycell transistor is depleted. As described above, since the edges 45 a ofthe Al wiring 45 are located immediately above those of the elementisolation film 34, using the Al wiring as a mask, the ion implantationcan be carried out with great accuracy. Thus, the threshold voltage ofthe memory cell transistor is lowered so that a ROM data is written.

In addition, in accordance with this invention, in the write of the ROMdata, since the metallic film (Al wiring 45) having higher processingaccuracy than the conventional photoresist, unlike the background art,it is not necessary to give sufficient allowance in order to avoidoccurrence of poor element isolation and to give the element isolationfilm a larger width than the processing limit. This permitsmicro-structuring.

Since a part of the interlayer insulating film 44 as well as theinterlayer insulating films 53, 52 and 51 on the Al wiring has beenetched, the ion-implanting can be carried out at low energy of 130 keVto 160 keV. This prevents the lateral diffusion of implanted ions, andhence permits the ion-implanting with higher accuracy.

Step 9: Although not illustrated, a pad portion is formed through thevia hole, a passivation film is formed on the entire surface. Thus, amask ROM with a desired program written is completed.

As described above, in accordance with this invention, the groove 47having a prescribed depth is formed in the surface of the wide Al wiring45A. For this reason, in the manufacturing process including provisionof the interlayer insulating film flattened using the SOG film, the SOGfilm 49 is not formed excessively thick on the wide Al wiring 45A. Owingto this, when this SOG 49 is etched back and thereafter when theinterlayer insulating film is etched, an etching remainder is notprovided. Thus, shortage of the opening when the interlayer insulatingfilm is etched is suppressed so that the via hole and the opening forwriting information in the ROM portion can be stably made. Thisstabilizes the characteristic and production yield. This also improvesthe uniformity in flattening the wafer surface.

Embodiment 3

Referring to the drawing, an explanation will be given of a thirdembodiment of this invention. The same manufacturing process as thesecond embodiment will be explained with reference to the drawings usedfor explaining the second embodiment.

The feature of the third embodiment resides in that after the step shownin FIG. 5C (step of forming the interlayer insulating film 44), as seenfrom FIG. 8A, the first Al wirings 45 are formed on the interlayerinsulating film 44 and slits are formed at regular intervals in the wideAl wiring 45A.

In this way, since the slits 60 are formed at regular intervals in thewide Al wiring 45A, the SOG film 49 which constitutes the interlayerinsulating film 51 is embedded in the slits, and hence is not formedexcessively thick on the periphery of the wide Al wiring 45A like theabove the second embodiment.

In this embodiment also, shortage of the opening when the interlayerinsulating film is etched is suppressed so that the via hole and theopening for writing information in the ROM portion can be stably made.This stabilizes the characteristic and production yield. This alsoimproves the uniformity in flattening the wafer surface.

Further, in this embodiment, unlike the second embodiment, after the Alwiring 45A has been formed, the groove(s) 47 is not formed by anindividual step in the Al wiring 45A. Instead of this, the slits 60 areformed when the Al wirings 45 and 45A are patterned. For this reason,the number of manufacturing steps is not increased.

The technical idea of this invention can be easily applied to the casewhere a larger number of layers of the metallic wiring is formed.

Further, in the step 3 of each embodiment, the gate electrode can beformed in any manner of forming a poly-Si film, patterning the poly-Si,and forming a silicide film on the poly-Si film.

Further, in each of the embodiments, although the P-type semiconductorsubstrate was used, an N-type semiconductor substrate or a well regionon the semiconductor substrate may be used.

Moreover, in each of the embodiments described above, the program waswritten in a manner of a depletion ion-implanting of lowering thethreshold voltage, but can be also written in a manner of boosting thethreshold value.

Further, the application filed of this invention should not be limitedto the method of writing a program in the mask ROM. This invention canbe applied to various products which experience the step of implantingimpurity ions using a photoresist as a mask, or using the photoresistand a metallic wiring as the mask.

In accordance with this invention, the protection film is formed on themetallic wiring, when the interlayer insulating films are etched usingthe metallic wiring as a mask. For this reason, the metallic wiring isnot etched and hence no deposit is formed on the side wall of theopening. Thus, the coverage when the passivation film is formed isimproved and hence the reliability of the device is also improved.

Further, in accordance with this invention, the groove or slit is formedin the surface of the wide metallic wiring. For this reason, the filmfor flattening which constitutes the interlayer insulating film isembedded in the groove or slits, and hence the film for flattening isnot deposited excessively thick. Thus, it is possible to prevent thecharacteristic deterioration and reduction of the production yield owingthe etching remainder.

1-7. (canceled)
 8. A semiconductor device comprising: a gate electrodeon a semiconductor substrate through a gate insulated film; source/drainregions to be adjacent to said gate electrode; a narrow metallic wiringand a wide metallic wiring on an lower layer interlayer insulating filmcovering said gate electrode; and an upper interlayer insulating filmformed to cover said metallic wirings and flattened, wherein a groove isformed in a surface of said wide metallic wiring.
 9. The semiconductordevice according to claim 8, wherein impurity ions are implanted into asurface of said semiconductor substrate with said interlayer insulatingfilms being etched by a prescribed amount using as a mask said metallicwirings and a photoresist formed thereabove.
 10. A semiconductor deviceaccording to claim 8, wherein slits are formed at regular intervals soas to subdivide said wide metallic wiring. 11-13. (canceled)
 14. Asemiconductor device comprising: a semiconductor substrate; a gateinsulated film on the semiconductor substrate; a gate electrode on thesemiconductor substrate through the gate insulated film; source/drainregions adjacent said gate electrode; a lower interlayer insulating filmcovering said gate electrode; a narrow metallic wiring and a widemetallic wiring on the lower interlayer insulating film covering saidgate electrode; and an upper interlayer insulating film formed to coversaid metallic wirings, wherein impurity ions are implanted into saidsemiconductor substrate with said interlayer insulating films beingetched using said metallic wirings and a photoresist formed thereaboveas masks, and a groove is formed on a surface of said wide metallicwiring.
 15. The semiconductor device of claim 14, wherein slits areformed on the device at regular intervals to subdivide said widemetallic wiring.
 16. The semiconductor device of claim 14, wherein saidlower interlayer insulating film comprises layers of a first siliconoxide film, a silicon nitride film, a poly-Si film and a second siliconoxide film.
 17. A semiconductor device comprising: a narrow metallicwiring; a wide metallic wiring; and a flattened interlayer insulatingfilm formed so as to cover said narrow metallic wiring and said widemetallic wiring; wherein a groove is formed on a surface of said widemetallic wiring.
 18. The semiconductor device according to claim 17further comprising a plurality of grooves formed at regular intervals soas to subdivide said wide metallic wiring.
 19. The semiconductor deviceaccording to claim 18 wherein impurity ions are implanted into a surfaceof a semiconductor substrate in accordance with write information in amask ROM.
 20. The semiconductor device according to claim 19 wherein thenarrow metallic wiring and the wide metallic wiring are formed so as tosurround a region into which the impurity ions are implanted.
 21. Thesemiconductor device according to claim 17 wherein impurity ions areimplanted into a surface of a semiconductor substrate in accordance withwrite information in a mask ROM.
 22. The semiconductor device accordingto claim 21 wherein the narrow metallic wiring and the wide metallicwiring are formed so as to surround a region into which the impurityions are implanted.